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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14000UB Dual 3-Input NOR" Gate Plus Inverter The MC14000UB dual 3-input NOR gate plus inverter is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. * * * * Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Swing Independent of Fanout Pin-for-Pin Replacement for CD4000UB L SUFFIX CERAMIC CASE 632 P SUFFIX PLASTIC CASE 646 MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage D SUFFIX SOIC CASE 751A II I I IIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII Value Unit V V - 0.5 to + 18.0 Vin, Vout lin, lout PD Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg TL - 65 to + 150 260 ORDERING INFORMATION MC14XXXUBCP MC14XXXUBCL MC14XXXUBD Plastic Ceramic SOIC TA = - 55 to 125C for all packages. _C _C LOGIC DIAGRAM 3 4 5 11 12 10 6 Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C CIRCUIT SCHEMATIC VDD 3 14 11 12 13 8 13 8 9 VDD = PIN 14 VSS = PIN 7 4 9 5 PIN ASSIGNMENT NC NC IN 1A IN 2A IN 3A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3B IN 2B IN 1B OUTB OUTC IN 1C VSS 76 10 OUTA VSS NC = NO CONNECTION REV 3 1/94 (c)MC14000UB Motorola, Inc. 1995 2 MOTOROLA CMOS LOGIC DATA II I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I II II II II III I II II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I II II II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I II II II III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I II II II III I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Ch ii Symbol S bl VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 -- Min -- -- -- - 55_C 25_C + 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Ui Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- "1" Level VOH Vin = 0 or VDD 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 -- -- -- 5.0 10 15 4.95 9.95 14.95 -- -- -- Vdc Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) "0" Level VIL Vdc 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- 2.25 4.50 6.75 2.75 5.50 8.25 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- "1" Level VIH Vdc 4.0 8.0 12.5 4.0 8.0 12.5 4.0 8.0 12.5 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 1.2 - 0.25 - 0.62 - 1.8 0.64 1.6 4.2 -- -- -- -- -- - 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8 - 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 -- -- -- -- -- Sink IOL mAdc Input Current Iin 0.1 -- 0.00001 5.0 0.1 7.5 1.0 -- Adc pF Input Capacitance (Vin = 0) Cin Quiescent Current (Per Package) IDD 5.0 10 15 5.0 10 15 0.25 0.5 1.0 0.0005 0.0010 0.0015 0.25 0.5 1.0 7.5 15 30 Adc Total Supply Current** (Dynamic plus Quiescent, Per Gate, CL = 50 pF) IT IT = (0.3 A/kHz) f + IDD/N IT = (0.6 A/kHz) f + IDD/N IT = (0.8 A/kHz) f + IDD/N Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in H (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14000UB 3 Vout , OUTPUT VOLTAGE (Vdc) 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 5.0 Vdc c 10 Vdc c b ID , DRAIN CURRENT (mAdc) c a b a ONE INPUT ONLY AND INVERTER b TWO INPUTS c THREE INPUTS 8.0 ID = 15 Vdc 6.0 4.0 2.0 0 Vout , OUTPUT VOLTAGE (Vdc) III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII II III II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- Typ # 180 90 65 100 50 40 115 55 40 Max 360 180 130 200 100 80 230 110 80 Unit ns Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 30 ns tPLH, tPHL = (0.66 ns/pF) CL + 22 ns tPLH, tPHL = (0.50 ns/pF) CL + 15 ns tPLH, tPHL ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 20 ns 14 PULSE GENERATOR INPUT OUTPUT 7 VSS CL OUTPUT tTHL INPUT tPHL 90% 50% 10% tTLH 90% 50% 10% tPLH VOH VOL 20 ns VDD VSS Figure 1. Switching Time Test Circuit and Waveforms 16 VDD = 15 Vdc 14 a TA = 25C 16 VDD = 15 Vdc 14 12 10 Vdc 10 8.0 6.0 4.0 a 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc) b 5.0 Vdc a b a b a TA = + 125C b TA = - 55C UNUSED INPUTS CONNECTED TO VSS b a ID = 10 Vdc 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc) Figure 2. Typical Voltage and Current Transfer Characteristics Figure 3. Typical Voltage Transfer Characteristics versus Temperature MC14000UB 4 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01 -A- 14 9 -B- 1 7 C L -T- SEATING PLANE K F D 14 PL G 0.25 (0.010) M N J TA S 14 PL M 0.25 (0.010) M TB S DIM A B C D F G J K L M N P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 8 B 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 A F C N H G D SEATING PLANE L J K M MOTOROLA CMOS LOGIC DATA MC14000UB 5 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 -B- 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14000UB 6 *MC14000UB/D* MOTOROLA CMOS LOGIC DATA MC14000UB/D |
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